![]() ![]() The fan-out of CMOS devices is usually greater than 50 because CMOS input current requirements are on the order of picoamps. Doubling the supply voltage more than doubles the speed of a CMOS gate. Typical delay times are 60 nsec for 5-V logic, 25 nsec operating at 10 V. The propagation delay times for CMOS devices are significant because of their high output The input is usually just modeled as a capacitor. In contrast, for TTL, there is no input impedance defined. The output impedance depends on the particular device, and is on the order of 1 kΩ, for either state. For example, the input impedance, in either state, of CMOS gates is typically 10 12 Ω. Performance factors vary depending on the logic family. Resistive loading reduces noise margins and output voltages. Resistive loading is present when the load impedance contains a resistive component, such as that associated with other logic devices. Thereby lengthening propagation delay times and slowing operation speed. The effect of capacitive loads is to lengthen the rise and fall times of signals, This external load capacitance component can be from other logic devices, stray wiring capacitance, or similar factors. There is capacitive loading if the load on the output of a gate has a capacitive component. The usual practice to prevent these current spikes from appearing as noise is to add one decoupling capacitor (0.01 to 0.1 ♟) from power to ground near the IC pins for each five to ten IC packages.Īny loads on the outputs of gates degrade the output signal. The largest spike happens in the LOW-to-HIGH transition. The result is current spikes (narrow pulses) in the power supply line. ![]() However, the chip draws an additional burst of current during the transition when the gate output changes state. When the output is LOW, the device draws a different constant supply current, 12 mA for the 7400 IC. When the output of a TTLĭevice is HIGH, the IC draws a constant supply current, 4 mA for a 7400 NAND gate. Reference voltage level called the threshold voltage.Ī phenomenon associated with TTL devices is current spiking. Consequently, the delay time is measured with respect to a Second, the input voltage to a gate need only reach the threshold voltage level before the device begins to change state. The fall time is the period required for the signal to fall from 90% to 10% of its initial value. The time needed for a signal to rise from 10% to 90% of its final value is called the rise time. The transitions between HIGH and LOW voltage levels have nonzero rise and fall times. The time span between when the input and outputĬhange states isn’t a satisfactory measure of the delay time for two reasons.įirst, the input signals to gates and the output signals produced by gates don’t resemble the idealized pulses studied in theory. In all practical gates, there’s a time lag between an input change and the corresponding output response. The propagation delay time for a gate specifies how long it takes the output to respond to a change in an input. The lower value of the two fanout values determines the fanout of the gate. Exceeding these fan-out limits may cause incorrect voltage levels at the output. A typical TTL gate can source 400 ♚ of current and can sink 16 mA. For logic 0, at most 1.6 mA flows from the input which the driving output must sink or accept.īy convention, the current flowing into an input or output is considered positive while a current flowing out of an input or output is considered negative. Typically at most 40 ♚ flows into an input at logic 1 and the driving output must provide this current. The nature of TTL gates dictates the use of two different fanout values, one for HIGH outputs and one for LOW outputs. A standard load is defined as the amount of current necessary to drive an input of another gate in the same logic family. TTL NAND gates typically provide 1, 2, 4, or 8 inputs.įan-out specifies how many standard loads the output of a gate can drive without a problem. Physical considerations limit fan-in, but practicalities such as the number of pins on IC packages generally are more important. Fan-in is the maximum number of inputs a gate can handle. Still, there is a lot of TTL around, so both must be considered.Įach logic family is characterized by several important parameters. ![]() TTL consumes far more power than CMOS, which is one reason CMOS has eclipsed TTL as the dominant technology. TTL employs bipolar junction transistor technology while CMOS uses the field-effect transistor concept at the input. Transistor-transistor logic (TTL) and complementary metal oxide semiconductor (CMOS) logic are the principal types of integrated circuit-based logic gates implemented in digital circuitry. ![]()
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